Video Line Selector

Electronic Schematics > Video and TV > Video Line Selector

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There are many video line selecter projects from of old, most line selecters are composed with a sync-separator and some counter ICs. In this project, all of counter/trigger function are processed by a microcontroller without external counter. Therefore, the circuit diagram could be very simple and it has many function.

Compsite sync pulses separated from input video signal are tied to external interrupt of an AVR and a flip-flop. Processing trigger output only software cannot avoid propagation delay and jitter, so that made the trigger edge pass through to the trigger output directly. Sync separator is composed by discrete parts, however, LM1881 is recommended if it is in stock. Test pins are for monitoring the clamped wave form.

Foreground task processes only user interface. Counting incoming syncs and trigger control are procecced by interrupt driven background tasks. AVR has very high performance, it will able to be implemented some additional functions. Any customized trigger mode or superimposing line marker will easy to implement with modifying the firmware or expanding some external components.

Line counting

First, 16 bit timer/counter is initialized as free running counter with 1.25MHz source clock and compare register is set to 65. The value will reach 79 while a horizontal period. The line counting process is driven by external interrupt (INT1). In this interrupt, when timer/counter has exceeded 60 (3/4H), the timer/counter is cleared and line counter is increased. If timer/counter is less than 60, the interrupt is half-H pulse, the line counter is not updated.

Trigger

After line counter is updated, if the value (next line) matches trigger line, trigger request flag is set. Compare match interrupt (timer/counter maches 65) is occured every 10µs before next line start. In this interrupt, if the trigger request flag is set, reset to external flip-flop is released and next sync edge will pass through the flip-flop. The flip-flop is reset agan by the external interrupt process. The trigger pulse width is approx. 2µs.

Detecting vertical sync pulse

8µs after external interrupt occured, sync level is sampled and stored it into shift register (left shifted). If the interrupt is at half-H, exit with no process. If it is start of line, compare the value of shift register and 0b11111110 (sync pattern at start of vertical sync). Only line 4 in odd field will match this condition. When the vertical sync is detected, set line conter to 4. This process is before updating line counter.

Detecting no signal

If no sync is detected for 20ms, timer/counter overflow interrupt will occure. In this interrupt, no signal flag is set and the condition is informed main task. The no signal flag is cleared by external interrupt (INT1).

Connect composite or Y video signal to input jack. When path torough the video signal to any other equipment, intrenal tremination resister must be disconnected. Trigger output is connected to oscilloscope as a trigger source (rise edge).

UP/DOWN buttons increase/decrease trigger line number. When hold the button for 0.4sec, the value is changed quickly. If the value reaches end of field, jump to next field (only odd/even mode). Non-interlaced signal, such as TV game and stilled video signal, does not have even field, so that trigger at even field will not generated. Trigger mode is changed by MODE button. Available trigger modes are as follows: